    M1 (LoOut PIN VDD\- VDD\-) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M0 (HiOut PIN VDD\+ VDD\+) PMOS_VTL w=180.0n l=50n as=1.89e-14 \
        ad=1.89e-14 ps=390.0n pd=390.0n ld=105n ls=105n m=1
    M3 (LoOut NIN VSS\- VSS\-) NMOS_VTL w=90n l=50n as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M2 (HiOut NIN VSS\+ VSS\+) NMOS_VTL w=90n l=50n as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
ends DelVGate
// End of subcircuit definition.
